Chip design should be open. All of it.

Every other field of engineering opened up. Software has open source, public repositories, and a portfolio culture where a stranger can read your work and hire you on it. Machine learning publishes its models, its datasets, and its failures. Chip design went the other way: the tools cost more than a salary and are licensed under NDA, the process kits arrive under click-wrap, the best work of every engineer's career is legally invisible, and the knowledge lives inside companies you cannot enter without already having the experience they demand. It is the most closed engineering discipline on earth — and it guards the substrate everything else runs on.

That closure has a cost nobody itemizes. A graduate cannot prove they can close timing, because closing timing requires a license server. An engineer's decade of tapeouts compresses to bullet points an interviewer must take on faith. A researcher cannot reproduce a placement result, because the baseline was tuned behind a wall. The industry hires on evidence of having done the work while structurally preventing anyone outside it from producing that evidence. Every other field would call that a moat. Chip design calls it normal.

We think it is neither necessary nor permanent, and this platform is the argument.

• Open tools, run for real. Yosys, OpenROAD, OpenSTA, Magic, Netgen, Verilator, Xyce — the flows here run the open stack end to end, from RTL and schematics to DRC-clean GDSII, and map every stage to its Synopsys, Cadence, and Siemens counterpart by name. Fluency transfers; the license wall does not survive the transfer.
• Open education, to an industrial bar. The training takes a graduate with zero commercial-EDA experience through digital, analog, and mixed-signal design — verification, timing, physical design, signoff, power, interfaces — with every practical executed on real flows, not simulated screenshots. What was apprenticeship folklore becomes a syllabus anyone can start tonight.
• Open evidence, checkable by strangers. Every claim here traces to tool output: a green stage means the tool exited clean on this run, and a credential is awarded only by re-verifying the runs, the signoff verdicts, and the published artifacts behind it. Not "trust me" — here is the DRC report, file three.
• Open work, under your own name. The hub publishes chips as browsable artifacts, run evidence as datasets, and personalized model recipes that keep ownership of your data legible. The portfolio culture chip design never had, built as infrastructure.

Honesty is the whole method, so here is the honest boundary: the leading-edge nodes stay closed, the fabs stay expensive, and no manifesto changes that this year. The bet is different. Skills, proof, and community do not need a 3 nm PDK to be open — sky130 closes timing by the same physics — and once the evidence of ability is public, the industry's hiring wall loses its foundation. Software's openness did not start at the kernel of every commercial product either. It started where starting was possible, and it never gave the ground back.

If you design chips, teach someone. If you are learning, publish what you build — failures included, they are the valuable part. If you run a team, hire on checkable work instead of badge history, and watch your candidate pool change shape.

Everything in chip design is a guarded secret. That is exactly why opening it counts. Start with chapter one. It opens once you sign in — free, with GitHub — because your progress, your runs, and your credential belong to an account. The syllabus is open to everyone.