Datasets
Design data: layout databases, netlists, testbenches, waveform corpora, expert corrections and whole trajectories.
Nothing has been published here yet. This is the beginning of the catalog, not the end of a search.
Public benchmarks worth measuring against
Externally owned and externally hosted — nothing here is redistributed by ActGen. Layout-native sets come first, because that is the axis this platform is built for.
- CircuitNetPhysical design
An open dataset built for machine learning in EDA, containing features extracted from placed-and-routed designs.
Measures: Congestion prediction, DRC violation prediction and IR-drop prediction — the three questions a physical designer most wants answered before committing to a route.
Licence not verified here — check the upstream project before using or redistributing. Unverified is not the same as unrestricted.
- SkyWater SKY130 PDKLayout / GDSII
An open-source 130nm process design kit, with standard cells and the collateral needed to tape out.
Measures: Whether generated layout is manufacturable against a real, published process rather than an idealised one. The only entry here backed by a foundry.
Upstream licence: Apache-2.0. Verify at the source before redistributing.
- OpenROAD-flow-scriptsLayout / GDSII
The reference RTL-to-GDSII flow for OpenROAD, with a set of designs that run end to end on open PDKs.
Measures: Whether an agent can drive a complete flow to a GDSII that passes the flow’s own checks — not one stage in isolation.
Upstream licence: BSD-3-Clause. Verify at the source before redistributing.
- MacroPlacement (TILOS)Physical design
An open effort to reproduce and evaluate ML-based macro placement, including designs such as Ariane and NVDLA on open enablements.
Measures: Macro placement quality against published baselines — and, unusually, whether a claimed result reproduces at all.
Licence not verified here — check the upstream project before using or redistributing. Unverified is not the same as unrestricted.
- EPFL Combinational Benchmark SuiteRTL / netlist
A suite of combinational circuits maintained as a standard target for logic synthesis research.
Measures: Logic optimisation quality — size and depth after synthesis — on circuits the field already agrees on.
Upstream licence: MIT. Verify at the source before redistributing.
- OpenCoresRTL / netlist
A long-running community repository of open-source hardware IP cores in Verilog and VHDL.
Measures: Breadth: whether a tool copes with real third-party RTL written by many hands, rather than tidy in-house examples. Licences vary PER CORE and must be checked individually.
Licence not verified here — check the upstream project before using or redistributing. Unverified is not the same as unrestricted.
- CVDP (Comprehensive Verilog Design Problems)RTL / netlist
NVIDIA’s benchmark of Verilog design and verification problems, spanning single-shot and agentic workflows over real RTL engineering tasks.
Measures: Whether an AI can carry a hardware-design task end to end — spec comprehension, RTL authoring, debug, and verification — the design-problem axis this platform’s Open Layout Benchmark extends into physical layout.
Licence not verified here — check the upstream project before using or redistributing. Unverified is not the same as unrestricted.