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Start with short interactive and long-context requests, then design the system that serves them: prefill, KV state and autoregressive decode. Build a compute, memory, interconnect or control component; verify its numerical and physical behavior, integrate analog interfaces and software, and carry its limits through chip, package, host, rack and cluster design. Compare quality, TTFT/TPOT and useful output tokens per facility energy and cost, then publish a reproducible portfolio.

Prerequisites: Basic digital logic and circuits: flip-flops, transistors and op-amps. No previous EDA-tool or tapeout experience is required. Reading and chapter checks are free. Workspace and AI work use credits; review the displayed price and runtime limit before starting each practical, and reuse the project you are developing.

How it ends: with the credential on your profile, then the AI technical interview that opens paid work on the platform.

Practice mental model transfer via reasoning corrections: reconstruct the task-relevant architecture and context, ground it in artifacts, then show how it changes a decision and how to falsify it. One task on the workbench leads to the Signing Bench, with FIFO, analog and digital physical design examples. The purpose is to capture your intelligence in your day-to-day work as evidence a laboratory can evaluate on held-out work; measured training gains are not assumed.

Prerequisites: The ability to read a design in your domain and say what is wrong with it. The technical interview that opens paid work, or the Industrial Chip Design training, is the expected background; neither is enforced. Reading, the worked examples and the checks are free. The one task the tutorial runs uses credits as any run does; the bench’s authoring form opens on an approved signing-bench application.

How it ends: with the credential on your profile, then the AI technical interview that opens paid work on the platform.