Public evidence
Silicon verification findings
We run our AI verification flow on respected open-source silicon — digital RTL and analog/mixed-signal netlists — and publish what holds up. Every finding names the exact commit and gives you a reproduction you can check on the public code yourself — no trust in us required. Each one survived two independent adversarial refutations before it was published, and every report also states what it cleared, so a finding list is never read without the checks it passed.
3 reports · 6 confirmed findings.
SERV — bit-serial RISC-V CPU
Digital RTL2 findings@ 41e8aeeThe award-winning bit-serial RV32I RISC-V core, widely used and RISC-V-compliance tested for the M, C and Zicsr extensions.
- Correctness bugMRET discards mepc[1]: trap-return lands two bytes early with the C extension
- Correctness riskAn interrupt preempting MRET or a mepc/mtval CSR read vectors to MTVAL instead of MTVEC
lulu9312 Bandgap_Reference — sky130 self-biased BGR
Analog / mixed-signal2 findings@ 5f958bcAn open-source sky130 bandgap voltage reference: a self-biased current-mirror core (NMOS mirror XM1/XM2, PMOS mirror XM3/XM4/XM5) develops a PTAT current across R1 from a 2:1 BJT ratio and sums it with a CTAT Vbe to make ~1.2 V. The README states the output is “constant … irrespective of temperature and supply variations.”
- Design defectSelf-biased reference with no startup circuit — power-up relies on subthreshold leakage
- Design defectOutput tracks the supply at ~85 mV/V — the “reference” does not reject VDD
Mabrains Analog_blocks — sky130 bandgap / LDO / OTA
Analog / mixed-signal2 findings@ d67887aOpen-source sky130 analog IP from an analog design-services firm, carried through to layout with DRC/LVS scripts and datasheets: Banba-style bandgap references (1.8 V, 5 V, self-biased), Miller and folded-cascode LDOs, and Miller / folded-cascode OTAs. References and LDOs are power-management IP — the class a company like TI ships by the thousand.
- Design defectA duplicated port name ties the supply to ground: the pre-layout bandgap testbench measures a dead circuit
- Design riskThe 1.8 V bandgap’s OTA repeats a port name across eight files — the ground connection is silently dropped
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